1. Field of the Invention
The present invention concerns a protective element for protecting a semiconductor element, and a semiconductor device having the protective element.
2. Description of Related Art
In a semiconductor device having a substrate comprising a compound semiconductor, for example, GaAs as a substrate, a protective element of an n+-i-n+ configuration in which ion implanted from a cap layer (n+) to an epitaxial wafer having a cap layer with addition of an n type impurity at a high concentration to form an insulation region (i) in the direction of the thickness is sometimes used for protecting a semiconductor element such as a capacitor which is sensitive to electrostatic destruction.
Japanese Patent Laid-Open No. 2006-310512 describes a compound semiconductor switch circuit device having a protective element of an n+-i-n+ configuration for protecting a logic circuit of a monolithic microwave integrated circuit (MMIC) against electrostatic destruction (refer to reference numeral 200 in FIG. 5).
In the device of Japanese Patent Laid-Open No. 2006-310512, a non-doped stacked buffer layer, an n+-AlGaAs electron supply layer, a spacer layer, a non-doped InGaAs channel layer, a spacer layer, an n+-AlGaAs electron supply layer, a non-doped AlGaAs barrier layer, and an n+-GaAs cap layer are stacked successively in this order over a GaAs substrate. B+ ions are implanted to the semiconductor stack from above the cap layer (137) and a portion from the cap layer to the non-doped stacked buffer layer is insulated in the direction of the thickness to form an insulation region (50). Then, an interconnection metal layer in contact with an n+ impurity region is disposed on both sides of the insulation region to form a protective element of the n+-i-n+ configuration. It is described that the interconnection metal layer may be connected to the n+ impurity layer either by Schottky junction or ohmic contact (paragraph 0119). When a high voltage is applied across both ends of the protective element of such a configuration, electrostatic energy flows through the n+-i-n+ region and a semiconductor element such as a capacitor connected with the protective element can be protected against electrostatic destruction.
Techniques relevant to the present invention include patent documents, that is, Japanese Patent Laid-Open Nos. 2005-340549, 2008-010468, 2008-258261, and 2008-263146, details of which are to be described later.